This invention relates generally to memory cells and more particularly to memory cells having a memory region comprising material having a first state of substantial electrical nonconductivity programmable to a second state of substantial electrical conductivity in response to an electrical signal applied thereto.
As is known in the art, memory cells have a wide range of applications, for example use in programmable memory arrays such as PROMs and logic and gate arrays. One type of memory cell, known as a "vertical fuse" memory cell, is discussed in U.S. Pat. No. 4,499,557, issued on Feb. 12, 1985 to Scott Holmberg et al and assigned to Energy Conversion Devices, Inc., of Troy, Mich. Such vertical fuse memory cell comprises a memory region comprising amorphous silicon being nominally in a first, substantially electrically nonconducting state. The memory region is supported by a doped (typically with n-type dopant) epitaxial layer of a semiconductor body. The memory region is disposed on a metal contact set in the doped epitaxial layer. The metal contact typically comprises platinum and forms a Schottky junction with the doped epitaxial layer. A first input terminal of the memory cell, typically comprising a strip of a highly electrically conductive metal, such as aluminum, is disposed above the memory region in electrical communication therewith. A barrier layer, comprising a refractory metal such as titanium-tungsten (TiW), is disposed between the memory region and the aluminum strip, such barrier layer preventing aluminum atoms from diffusing into and damaging the silicon memory region. A second input terminal of the memory cell is formed in the doped epitaxial layer, and typically comprises a buried subcollector region of heavily doped (such as with n.sup.+ -type conductivity dopant) silicon.
Nominally, the first and second input terminals of the memory cell are electrically isolated from each other by the nominally electrically nonconductive memory region. Such nonconducting condition represents a first logic state of the memory cell. However, upon application of a suitable electrical programming signal between the first and second input terminals, the substantially electrically nonconducting state of the amorphous silicon of the memory region is nonresettably converted to a substantially electrically conducting state, thereby electrically coupling the first and second input terminals together through a low resistance, typically 100 ohms, and setting the memory cell to a second logic state.
While such a memory cell functions satisfactorily in some applications, the electrical programming signal, typically a current pulse, generates heat in the memory region and the Schottky metal contact. If the current pulse level is too high, sufficient heat will be generated to cause the metal of the Schottky contact to diffuse or migrate into the converted, electrically conducting silicon of the memory region. This increases the reverse leakage current of the Schottky diode comprising the metal contact. The total reverse leakage current for the array increases as additional individual memory cells are subsequently programmed. Since there are commonly many such memory cells (and hence Schottky diodes) in a typical memory array, such increased reverse leakage current results in a large leakage current drain from the memory array power supply, thereby reducing the current pulse amplitude which such power supply is able to provide for subsequently-programmed memory cells in the array. The programming current pulse level for the initially-programmed memory cells may be decreased to avoid this problem, but if such level is made too low, the substantially electrically nonconducting state of the memory region may not change to the substantially electrically conducting state; that is, the memory cell may not be properly programmed from the first logic state to the second logic state.